I2C Protocol Subtleties – Part 1

Jean J. White

This article is the initial in a series describing the more ‘subtle’ areas of the I2C Protocol, at first made by Philips.

Due to the fact you are looking at this collection, I am assuming you currently know what the I2C bus is, and you might be seeking to stay away from some discomfort when you require to use it in a project. If so, you’ve got occur to the suitable put. If not, I am going to be introducing some introductory I2C details soon at my website.

Just so we’re apparent, this collection will not involve coverage of the High-velocity mode, as this is considerably unique from the design and style and behavior of the ordinary 2-wire shared-bus implementation, and is also not that frequently employed. There is a good deal of superb reference materials readily available on the World-wide-web that covers this mode.

This is a quick listing of what will be included in the relaxation of the collection:

  • missing Commence
  • missing Halt
  • Recurring Commence
  • lacking info bits
  • lacking ACK/NAK
  • details immediately after NAK
  • back-to-again mistakes
  • pullup resistors
  • bus repeaters
  • implementation using a whole-hardware TWI or I2C peripheral
  • implementation utilizing a USI peripheral
  • implementation using a USART peripheral
  • SMBus discrepancies from I2C

Now, on to the fantastic things!

For this short article, we will focus on the 3 styles of implementations you will locate in types these days: comprehensive hardware, hardware/computer software combine, and full application (or ‘bit-bang’ as it is from time to time termed).

Many microcontrollers now, even some low-conclude units, contain a totally-hardware I2C peripheral. Atmel refers to theirs as TWI, Microchip phone calls theirs I2C other suppliers use comparable naming. When using a entirely-components strategy, it is basically difficult to create any kind of bus error unless you misunderstand how the peripheral operates or what a right I2C bus sequence ought to look like. In basic, even though, this solution involves the least in-depth being familiar with of the protocol by itself.

The USI peripheral found in some Atmel devices is a nominal-components layout that depends on software interaction to make it a total implementation. This versatile peripheral can truly be used for I2C, SPI and UART configurations, and is appropriate for lower-conclude products wherever including all a few peripherals would be price tag-prohibitive. While it necessitates additional coding than a TWI or entire-components I2C peripheral, it is in some strategies a lot more adaptable. This technique requres a much more in-depth understanding of the protocol, as you are liable for going from a single condition to the subsequent, and it is possible to go in the mistaken direction.

And finally, employing a 100% software solution requires a entire being familiar with of the I2C protocol. Nearly just about every microcontroller seller presents application notes and code illustrations for creating an I2C Learn gadget working with a pure-software alternative. In contrast to a UART, I2C is a clocked (fairly than timed) protocol, so interruptions in the execution of the protocol are tolerated nicely, enabling interrupts to be serviced without the need of worry for dropping information. The greatest pace of the software package-primarily based resolution is ultimately decided by the CPU clock velocity, and generally a Master implementation can effortlessly attain the 400KHz price.

A software package-primarily based implementation of a Slave machine is considerably more challenging. Without hardware assistance, the software package need to keep track of both equally the SDA and the SCL traces simultaneously in buy to detect clock edges and know positively the condition of the SDA line prior to the rise or fall of SCL. Detection of a Get started or Stop ailment will generally require the use of interrupts, otherwise the software program would want to be 100% consumed with checking SCL and SDA. Software-primarily based Slave implementations tend to be CPU-sure, necessitating a number of MIPS to realize even 100KHz procedure. Therefore, accurate software package-only Slave implementations may not even exist for some microcontroller families, and some others could not be able of achieving whole 100KHz bus velocity.

With this hardware and computer software basis having been laid, we will dive deeper into the protocol by itself in our upcoming report. Many thanks for looking through!

(Copyright 2010 Robert G. Fries)

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